1. Field
Aspects of the present disclosure relate generally to fixing hold violations, and more particularly, to fixing hold violations using metal-programmable cells.
2. Background
Flip-flops (e.g., D flip-flops) are commonly used in integrated circuits to capture data values from a data signal on active edges of an input clock signal. The active edges may be rising clock edges for a positive-edge triggered flip-flop or falling clock edges for a negative-edge triggered flip-flop.
In order for a flip-flop to properly capture a data value from the data signal, the data value needs to be stable at the input of the flip-flop for a time period before an active edge of the clock signal (referred to as setup time), and for a time period after the active edge of the clock signal (referred to as hold time). A hold violation occurs when the data value at the input of the flip-flop changes during the hold time of an active edge of the clock signal. The hold violation may be fixed by adding a delay to the data signal so that the data value at the input of the flip-flop changes outside the hold time of the active edge of the clock signal. Typically, the delay is added by inserting one or more buffers into a data path that routes the data signal to the input of the flip-flop.